The inventive concept relates to clock data recovery circuits, and more particularly, to clock data recovery circuits using a Pseudo Random Binary Sequence (PRBS) pattern.
Many contemporary electronic devices utilize one or more high-speed input/output (I/O) interfaces, such as a serial data link. Data is communicated (i.e., received and/or transmitted) via such high speed I/O interfaces at ever increasing rates. In order to coherently communicate data (e.g., data designated for communication via a particular channel), a high speed I/O interface (e.g., a receiver portion of a high speed I/O interface) typically requires a clock data recovery circuit.
In certain approaches to the communication of high speed data, a clock data recovery circuit may initially receive a so-called clock recovery (CR) pattern and an equalization (EQ) pattern. Using the CR and EQ patterns as initialization references, certain clock data recovery circuits may be configured (or prepared) to receive high speed data. The process of preparing a clock data recovery circuit to receive high speed data is referred to as training, and the CR and EQ patterns are respective training patterns. However, as performance demands placed upon contemporary electronic devices have increased, training approaches used by conventional clock data recovery circuits have proved too slow. That is, the delay engendered by the training of clock data recovery circuits is too long.
In contrast, certain communication approaches do not provide training pattern(s) to a clock data recovery circuit. Instead, high speed data is immediately provided. Such approaches eliminate the issue of undue training delay, but compared with properly trained clock data recovery circuits, the reliability of recovered data is degraded.